Type of integrated circuit
集成电路的类型
Sinclair ZX81 ULA
Sinclair ZX81 Ula
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.
栅极阵列是一种使用预制的芯片设计和制造的方法，该方法是使用预制的芯片，其组件随后通过自定义订单添加工厂中的金属互连层，这些芯片随后将其互连为逻辑设备（例如NAND GATES，人字拖等）。它在1980年代的半导体行业的动荡期间很受欢迎，到1990年代末，其用法下降了。
Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.
还采用了类似的技术来设计和制造模拟，模拟 - 数字和结构化阵列，但通常，这些阵列并不称为栅极阵列。
Gate arrays have also been known as uncommitted logic arrays ('ULAs'), which also offered linear circuit functions,[1] and semi-custom chips.[citation needed]
门阵列也被称为“未拨入的逻辑阵列（'ulas'），它也提供了线性电路功能，[1]和半定量芯片。[需要引用]
History [ edit ]
历史[编辑]
Development [ edit ]
开发[编辑]
Gate arrays had several concurrent development paths. Ferranti in the UK pioneered commercializing bipolar ULA technology,[2] offering circuits of"100 to 10,000 gates and above" by 1983.[3][4] The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from Rollei in 1972, expanding to"practically all European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to around 30 percent. Ferranti's"major competitors" were other British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering.[5] A contemporary initiative, UK5000, also sought to produce a CMOS gate array with"5,000 usable gates", with involvement from British Telecom and a number of other major British technology companies.[6]
门阵列有几个并发的开发路径。英国的Ferranti开创了商业化双极ULA技术，[2]到1983年提供“ 100至10,000大门”的电路。[3] [4]该公司在半定期芯片中的早期领先优势，涉及1972年Rollei的ULA集成电路的最初应用，并作为该技术的用户扩展到“实际上所有欧洲摄像头制造商”，导致该公司在整个1970年代在这个特定市场中的统治地位。但是，到1982年，多达30家公司开始与Ferranti竞争，将公司的市场份额降低到30％左右。费兰蒂（Ferranti）的“主要竞争对手”是其他英国公司，例如马可尼（Marconi）和普莱西（Plessey），这两家公司都有另一家英国公司Micro Circuit Engineering的许可技术。[5]一项当代倡议UK5000也试图生产一个带有“ 5,000可用大门”的CMOS门阵列，并与英国电信和许多其他主要英国技术公司一起参与。[6]
IBM developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally. Fairchild Semiconductor also flirted briefly in the late 1960s with bipolar arrays diode–transistor logic and transistor-transistor logic called Micromosaic and Polycell.[7]
IBM开发了1970年代末和1980年代初在大型机制造中使用的专有双极主片，但从未在外部商业化。Fairchild半导体还在1960年代后期用双极阵列二极管 - 晶体管逻辑和晶体管 - 透射术语逻辑称为Micromosaic和Polycell。[7]
CMOS (complementary metal–oxide–semiconductor) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp[8][9] in 1974 for International Microcircuits, Inc.[7] (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed 7.5 micron single-level metal CMOS technology and ranged from 50 to 400 gates. Computer-aided design (CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.
CMOS（互补的金属 - 氧化物 - 溶剂导体）技术为栅极阵列的广泛商业化打开了大门。第一个CMOS门阵列是由Robert Lipp [8] [9]于1974年开发的，用于国际MicroCircuits，Inc。[7]（IMI）由弗兰克·德弗斯（Frank Deverse），吉姆·塔特尔（Jim Tuttle）和前IBM员工查理·艾伦（Charlie Allen）创立的Sunnyvale Photo Mask商店。该第一产品线采用7.5微米的单层金属CMOS技术，范围从50到400个大门不等。当时计算机辅助设计（CAD）技术由于可用的处理功率低而非常基本，因此这些第一个产品的设计仅是部分自动化的。
This product pioneered several features that went on to become standard in future designs. The most important were: the strict organization of n-channel and p-channel transistors in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was somewhat tedious and error-prone due to the lack of good software tools.[7] IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer. Rubylith sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage; drawings were still manual and then"hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.
该产品开创了几个功能，这些功能继续成为未来设计的标准。最重要的是：在整个芯片上以2-3行对N通道和P通道晶体管的严格组织；并在网格上运行所有互连，而不是最小自定义间距，这是标准的。后来的创新与2层CMOS阵列的开发相结合时，为完全自动化铺平了道路。由于缺乏良好的软件工具，自定义这些第一部分有些乏味且容易出错。[7]IMI采用PC板开发技术，以最大程度地减少手动定制工作。当时的芯片是通过手动设计的，绘制所有组件并在精密栅格的薄膜板上互连，并使用彩色铅笔来描述每个加工层。然后将Rubylith片切割并去皮，以创建过程层的（通常）200倍至400倍的比例表示。然后将其缩减为制作1倍面膜。数字化而不是鲁布利斯的切割只是作为最新技术而来的，但最初仅删除了Rubylith阶段。图纸仍然是手动的，然后“手”数字化。同时，PC板已从定制的Rubylith转移到PC胶带进行互连。IMI创建了基本层的to cale摄影。使用逻辑门连接和PC磁带的贴花来互连这些门，可以用手动迅速将自定义电路用于这些相对较小的电路，并使用现有技术进行照相。
After a falling out with IMI, Robert Lipp went on to start California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson, and Brian Tighe. CDI quickly developed a product line competitive to IMI and, shortly thereafter, a 5-micron silicon gate single-layer product line with densities of up to 1,200 gates. A couple of years later, CDI followed up with"channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first-level metal interconnect. This increased chip densities by 40%, significantly reducing manufacturing costs.[8]
与IMI脱颖而出后，罗伯特·利普（Robert Lipp）于1978年与两个无声伙伴伯尼·阿隆森（Bernie Aronson）和布莱恩·蒂格（Brian Tighe）一起创立了加利福尼亚设备，公司（CDI）。CDI迅速开发了与IMI竞争的产品线，此后不久，一条5微米硅门单层产品线的密度高达1200个门。几年后，CDI跟进了“无通道”栅极阵列，该阵列降低了由更复杂的硅底层造成的行阻塞，该硅底层层较复杂，该硅底层将单个晶体管连接与常见逻辑函数所需的位置进行了预订，从而简化了一级金属互连。这使芯片密度提高了40％，大大降低了制造成本。[8]
Innovation [ edit ]
创新[编辑]
Ferranti ULA 2C210E on a Timex Sinclair 1000 motherboard
Ferranti ULA 2C210E TIMEX SINCLAIR 1000主板
Early gate arrays were low-performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low-power applications such as watch chips and battery-operated portable instrumentation, not performance. They were also well under the performance of the existing dominant logic technology, transistor–transistor logic. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as"garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the CB craze in the 1970s as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.
与最先进的N-MOS技术相比，早期的门阵列效果低，相对较大且昂贵，然后用于定制芯片。CMOS技术是由非常低的功率应用程序（例如手表芯片和电池供便携式仪器而不是性能）驱动的。它们也很好，在现有的主要逻辑技术，晶体管 - 透射逻辑的性能下。但是，在许多利基应用程序中，它们是无价的，尤其是在低功率，尺寸降低，便携式和航空航天应用以及市场敏感产品的情况下。即使这些小阵列也可以替换充满晶体管 - 透射逻辑门的板，如果性能不是问题。一个常见的应用是组合了许多较小的电路，这些电路支持板上较大的LSI电路被亲切地称为“垃圾收集”。而且，开发和自定义工具的低成本使该技术可用于最适中的预算。早期的门阵列在1970年代在CB热潮中发挥了很大作用，也是引入其他后来生产的产品（例如调制解调器和手机）的工具。
By the early 1980s, gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; the technology became"hot" when in 1981 IBM introduced its new flagship 3081 mainframe with CPU comprising gate arrays. They were used in a consumer product, the ZX81, and new entrants to the market increased visibility and credibility.[10][11]
到1980年代初，Gate阵列开始将其利基应用程序迁移到通用市场。技术和市场的几个因素正在融合。大小和性能正在增加；自动化正在成熟；1981年，IBM推出了其新的旗舰3081大型机，其中包括GATE阵列时，该技术变得“热”。它们用于消费产品，ZX81和新进入市场的新进入者都提高了知名度和信誉。[10] [11]
In 1981, Wilfred Corrigan, Bill O'Meara, Rob Walker, and Mitchell"Mick" Bohn founded LSI Logic.[12] Their initial intention was to commercialize emitter coupled logic gate arrays, but discovered the market was quickly moving towards CMOS. Instead, they licensed CDI's silicon gate CMOS line as a second source. This product established them in the market while they developed their own proprietary 5-micron 2-layer metal line. This latter product line was the first commercial gate array product amenable to full automation. LSI developed a suite of proprietary development tools that allowed users to design their own chip from their own facility by remote login to LSI Logic's system.
1981年，Wilfred Corrigan，Bill O'Meara，Rob Walker和Mitchell“ Mick” Bohn创立了LSI逻辑。[12]他们最初的意图是将发射极耦合的逻辑门阵列商业化，但发现市场迅速朝着CMO迈进。取而代之的是，他们将CDI的硅门CMOS系列授权为第二来。该产品在他们开发自己的专有5微米2层金属系列时在市场上建立了它们。后一种产品系列是第一个可随机自动化的商业门阵列产品。LSI开发了一套专有开发工具，使用户可以通过远程登录到LSI Logic的系统从自己的设施设计自己的芯片。
Sinclair Research ported an enhanced ZX80 design to a ULA chip for the ZX81, and later used a ULA in the ZX Spectrum. A compatible chip was made in Russia as T34VG1.[13] Acorn Computers used several ULA chips in the BBC Micro, and later a single ULA for the Acorn Electron. Many other manufacturers from the time of the home computer boom period used ULAs in their machines. The IBM PC took over much of the personal computer market, and the sales volumes made full-custom chips more economical. Commodore's Amiga series used gate arrays for the Gary and Gayle custom chips, as their code names may suggest.
Sinclair Research将增强的ZX80设计移植到ZX81的ULA芯片上，后来在ZX频谱中使用了ULA。在俄罗斯用T34VG1制作了兼容的芯片。[13]橡子计算机在BBC微型中使用了多个ULA芯片，然后在橡子电子中使用了单个ULA。从家用计算机繁荣时期起，许多其他制造商在其机器中使用了Ulas。IBM PC接管了个人计算机市场的大部分，销售量使完整的芯片更加经济。Commodore的Amiga系列使用了Gary和Gayle自定义芯片的门阵列，正如其代码名称所建议的那样。
In an attempt to reduce the costs and increase the accessibility of gate array design and production, Ferranti introduced in 1982 a computer-aided design tool for their uncommitted logic array (ULA) product called ULA Designer. Although costing £46,500 to acquire, this tool promised to deliver reduced costs of around £5,000 per design plus manufacturing costs of £1-2 per chip in high volumes, in contrast to the £15,000 design costs incurred by engaging Ferranti's services for the design process.[14] Based on a PDP-11/23 minicomputer running RSX/11M, together with graphical display, keyboard,"digitalizing board", control desk and optional plotter, the solution aimed to satisfy the design needs of gate arrays from 100 to 10,000 gates, with the design being undertaken entirely by the organisation acquiring the solution, starting with a"logic plan", proceeding through the layout of the logic in the gate array itself, and concluding with the definition of a test specification for verification of the logic and for establishing an automated testing regime. Verification of completed designs was performed by"external specialists" after the transfer of the design to a"CAD center" in Manchester, England or Sunnyvale, California, potentially over the telephone network. Prototyping completed designs took an estimated 3 to 4 weeks. The minicomputer itself was also adaptable to run as a laboratory or office system where appropriate.[15]
为了降低成本并提高门阵列设计和生产的可访问性，Ferranti于1982年推出了一种计算机辅助设计工具，该工具用于其未建立的逻辑阵列（ULA）产品，称为ULA Designer。尽管收购成本为46,500英镑，但该工具承诺将降低每张设计约5,000英镑的成本，加上每筹码1-2英镑的高量的制造成本，与使费兰蒂（Ferranti）的设计用于设计过程所产生的15,000英镑的设计成本相比。[14]基于运行RSX/11M的PDP-11/23最小计算机，以及图形显示，键盘，“数字化板”，Control Desk和可选绘图仪，旨在满足100到10,000个门的设计需求，从而使设计的设计需求从组织中完全通过“逻辑计划”开始，并通过“逻辑计划”来进行，并通过“逻辑计划”进行，并通过逻辑计划，沿着逻辑播放，沿着逻辑播放，该逻辑是通过“ logic”计划进行的。用于验证逻辑和建立自动测试制度的测试规范。将设计转移到曼彻斯特，英格兰，英格兰或加利福尼亚州桑尼维尔的“外部专家”或加利福尼亚州的“ CAD中心”之后，对完成的设计进行了验证。原型设计的设计估计需要3到4周。微型计算机本身也可以在适当的情况下适应实验室或办公室系统。[15]
Ferranti followed up on the ULA Designer with the Silicon Design System product based on the VAX-11/730 with 1 MB of RAM, 120 MB Winchester disk, and utilising a high-resolution display driven by a graphics unit with 500 KB of its own memory for"high speed windowing, painting, and editing capabilities". The software itself was available separately for organisations already likely to be using VAX-11/780 systems to provide a multi-user environment, but the"standalone system" package of hardware and software was intended to provide a more affordable solution with a"faster response" during the design process. The suite of tools involved in the use of the product included logic entry and test schedule definition (using Ferranti's own description languages), logic simulation, layout definition and checking, and mask generation for prototype gate arrays. The system also sought to support completely auto-routed designs, utilising architectural features of Ferranti's auto-routable (AR) arrays to deliver a"100-percent success auto-layout system" with this convenience incurring an increase in silicon area of approximately 25 percent. [16]
Ferranti以Vax-11/730的硅设计系统产品在ULA设计师身上进行了跟进，其中包括1 MB RAM，120 MB Winchester磁盘，并利用由图形单元驱动的高分辨率显示器，其图形单元具有500 kb的图形单元，其自己的内存为“高速窗口，绘画和编辑能力”。该软件本身可单独使用，可用于已经可能使用VAX-11/780系统提供多用户环境的组织，但是在设计过程中，“独立系统”软件包的“独立系统”包旨在提供更实惠的解决方案，并具有“更快的响应”。使用产品涉及的工具套件包括逻辑输入和测试时间表定义（使用Ferranti自己的描述语言），逻辑模拟，布局定义和检查以及原型门阵列的掩码生成。该系统还试图利用Ferranti自动折线（AR）阵列的建筑特征来支持全自动设计的设计，以提供“ 100％的成功自动延入系统”，并具有这种便利性，从而增加了大约25％的硅面积。[16]
Other British companies developed products for gate array design and fabrication. Qudos Limited, a spin-off from Cambridge University, offered a chip design product called Quickchip available for VAX and MicroVAX II systems and as a complete $11,000 turnkey solution, providing a suite of tools broadly similar to those of Ferranti's products including automatic layout, routing, rule checking and simulation functionality for the design of gate arrays. Qudos employed electron beam lithography,[17] etching designs onto Ferranti ULA devices that formed the physical basis of these custom chips. Typical prototype production costs were stated as £100 per chip.[18] Quickchip was subsequently ported to the Acorn Cambridge Workstation, with a low-end version for the BBC Micro,[19] and to the Acorn Archimedes.[20]
其他英国公司开发了用于门阵列设计和制造的产品。剑桥大学的衍生产品Qudos Limited提供了一种名为QuickChip的芯片设计产品，可用于VAX和Microvax II系统，作为一个完整的11,000美元交钥匙解决方案，提供了一套与Ferranti产品相似的工具，包括自动布局，路由，路由，规则检查和模拟Gate Drays Designeration。Qudos使用电子束光刻，[17]在构成这些自定义芯片的物理基础的Ferranti Ula设备上蚀刻设计。典型的原型生产成本表示为每芯片100英镑。[18]QuickChip随后被移植到Acorn Cambridge Workstation，其低端版本用于BBC Micro，[19]和Acorn Archimedes。[20]
Alternatives [ edit ]
替代方案[编辑]
Indirect competition arose with the development of the field-programmable gate array (FPGA). Xilinx was founded in 1984, and its first products were much like early gate arrays, slow and expensive, fit only for some niche markets. However, Moore's Law quickly made them a force and, by the early 1990s, were seriously disrupting the gate array market.
间接竞争是随着现场编程栅极阵列（FPGA）的发展而产生的。Xilinx成立于1984年，其第一批产品就像早期的登机阵列一样缓慢而昂贵，仅适合某些利基市场。但是，摩尔的定律迅速使它们成为一支力量，到1990年代初期，摩尔的定律正在严重破坏门阵列市场。
Designers still wished for a way to create their own complex chips without the expense of full-custom design, and eventually, this wish was granted with the arrival of not only the FPGA, but complex programmable logic device (CPLD), metal configurable standard cells (MCSC), and structured ASICs. Whereas a gate array required a back-end semiconductor wafer foundry to deposit and etch the interconnections, the FPGA and CPLD had user-programmable interconnections. Today's approach is to make the prototypes by FPGAs, as the risk is low and the functionality can be verified quickly. For smaller devices, production costs are sufficiently low. But for large FPGAs, production is very expensive, power-hungry, and in many cases, do not reach the required speed. To address these issues, several ASIC companies like BaySand, Faraday, Gigoptics, and others offer FPGA to ASIC conversion services.
设计师仍然希望能够创建自己的复杂芯片，而无需花费全面设计的费用，最终，这种愿望不仅是FPGA的到来，而且是复杂的可编程逻辑设备（CPLD），金属可配置的标准单元（MCSC）和结构化的ASIC。栅极阵列需要一个后端半导体晶圆铸造厂来沉积和蚀刻互连，而FPGA和CPLD具有用户可编程的互连。当今的方法是制作FPGA的原型，因为风险很低，并且可以迅速验证功能。对于较小的设备，生产成本足够低。但是对于大型FPGA来说，生产非常昂贵，渴望，在许多情况下，没有达到所需的速度。为了解决这些问题，Baysand，Faraday，Gigoptics等几家ASIC公司为ASIC转换服务提供了FPGA。
Decline [ edit ]
下降[编辑]
While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling recessions during the 1980s that created a boom-bust cycle. The 1980 and 1981–1982 general recessions were followed by high-interest rates that curbed capital spending. This reduction played havoc on the semiconductor business, which at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast-moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on production revenues.[8]
在市场蓬勃发展的同时，该行业的利润缺乏。半导体在1980年代经历了一系列滚动衰退，从而产生了繁荣的周期。1980年和1981 - 1982年的一般衰退之后，高利率遏制了资本支出。这种减少对半导体业务造成了严重破坏，当时该业务高度依赖于资本支出。制造商迫切希望在快速发展的行业中保持富有现代化的现代化，使其变得竞争激烈。市场上的许多新进入者都将门阵列价格降低到硅制造商的边际成本。LSI Logic和CDI等制片公司在销售设计服务和计算机时间而不是生产收入方面幸存下来。[8]
As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed-signal circuits and was later acquired by Cypress Semiconductor in 2001; CDI closed its doors in 1989; and LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.[21]
截至21世纪初期，由于出于成本或绩效原因进行的FPGA转换驱动，门阵列市场是其以前自我的残余。Imi从门阵列中移出混合信号电路，后来由赛普拉斯半导体在2001年获得。CDI于1989年关闭了大门。LSI逻辑放弃了市场支持标准产品，并最终被Broadcom收购。[21]
Design [ edit ]
设计[编辑]
A gate array is a prefabricated silicon chip with most transistors having no predetermined function. These transistors can be connected by metal layers to form standard NAND or NOR logic gates. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. The creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a printed circuit board.
栅极阵列是一种预制的硅芯片，大多数晶体管没有预先确定的函数。这些晶体管可以通过金属层连接以形成标准的NAND或也不是逻辑门。然后可以将这些逻辑门进一步互连到相同或更高版的金属层上的完整电路中。具有指定功能的电路的创建是通过在制造过程后期将最终层或金属互连层添加到芯片的，从而可以根据需要定制芯片的功能。这些层类似于印刷电路板的铜层。
The earliest gate arrays comprised bipolar transistors, usually configured as high-performance transistor–transistor logic, emitter-coupled logic, or current-mode logic logic configurations. CMOS (complementary metal–oxide–semiconductor) gate arrays were later developed and came to dominate the industry.
最早的门阵列包含双极晶体管，通常配置为高性能晶体管 - 透射术逻辑，发射器耦合的逻辑或电流模式逻辑逻辑配置。CMOS（互补的金属 - 氧化物 - 溶剂导体）后来开发出来，并占据了该行业的主导地位。
Gate array master slices with unfinished chips arrayed across a wafer are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than standard cell or full custom design. The gate array approach reduces the non-recurring engineering mask costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced — the same test fixtures can be used for all gate array products manufactured on the same die size. Gate arrays were the predecessor of the more complex structured ASIC; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.
Gate Array Master Slices带有未完成的芯片片段的片段，通常会预制并大量储存，无论客户订单如何。根据单个客户规格的设计和制造可以在短时间内完成，而不是标准单元格或完整的自定义设计。Gate Array方法降低了非经常性工程面具的成本，因为需要制作更少的自定义面罩。此外，制造测试工具提前时间和成本降低了 - 所有以相同的模具尺寸生产的栅极阵列产品都可以使用相同的测试固定装置。栅极阵列是更复杂的结构化ASIC的前身；与门阵列不同，结构化的ASIC倾向于包括预定义或可配置的记忆和/或模拟块。
An application circuit must be built on a gate array that has enough gates, wiring, and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a crossbar switch requires much more routing than a systolic array with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.
必须在具有足够大门，接线和I/O销的门阵列上构建应用电路。由于需求有所不同，门阵列通常会出现在家庭中，而大型成员拥有更多的所有资源，但相应的昂贵。尽管设计师可以很容易地计算出需要多少个大门和I/OS引脚，但即使在具有相同逻辑量的设计中，所需的路由轨道的数量也可能有很大差异。（例如，横梁开关比具有相同门数的收缩期阵列需要更多的路由。）由于未使用的路由轨道增加了零件的成本（并降低零件的性能（并降低性能），而无需提供任何福利，因此Gate Array制造商试图提供足够的轨道，以便大多数适合Gates和I/O PINS的设计符合。这取决于诸如从租金规则或现有设计实验的估计决定。
The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However, this style is often a viable approach for low production volumes.
与ASIC设计的其他方法相比，门阵列的主要缺点是它们的密度和性能较低。但是，这种样式通常是低产量量的可行方法。
Uses [ edit ]
使用[编辑]
Gate arrays were used widely in the home computers in the early to mid 1980s, including in the ZX81, ZX Spectrum, BBC Micro, Acorn Electron, Advance 86, and Commodore Amiga.
栅极阵列在1980年代初期至中期广泛使用，包括在ZX81，ZX Spectrum，BBC Micro，Acorn Electron，Advance 86和Commodore Amiga中使用。
In the 1980s, the Forth Novix N4016 and HP 3000 Series 37 CPUs, both stack machines were implemented by gate arrays as were some graphic terminal functions.[22][23] Some supporting hardware in at least 1990s DEC and HP servers was implemented by gate arrays.[24][25]
在1980年代，Forth Novix N4016和HP 3000系列37 CPU，这两个堆栈机都是由Gate阵列和某些图形终端函数实现的。[22] [23] [23]至少在1990年代的DEC和HP服务器中，一些支持硬件由门阵列实现。[24] [25]
References [ edit ]
参考[编辑]
Further reading [ edit ]
进一步阅读[编辑]
